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1 ispgdx 80va in-system programmable 3.3v generic digital crosspoint functional block diagram features ? in-system programmable generic digital crosspoint family advanced architecture addresses programmable pcb interconnect, bus interface integration and jumper/switch replacement ??ny input to any output?routing ?fixed high or low output option for jumper/dip switch emulation ?space-saving pqfp and bga packaging ?dedicated ieee 1149.1-compliant boundary scan test high performance e 2 cmos technology ?3.3v core power supply ?3.0ns input-to-output/3.0ns clock-to-output delay 250mhz maximum clock frequency ttl/3.3v/2.5v compatible input thresholds and output levels (individually programmable) ?low-power: 16.5ma quiescent icc ?24ma i ol drive with programmable slew rate control option pci compatible drive capability ?schmitt trigger inputs for noise immunity ?electrically erasable and reprogrammable ?non-volatile e 2 cmos technology ispgdxv offers the following advantages ?3.3v in-system programmable using boundary scan test access port (tap) ?change interconnects in seconds flexible architecture ?combinatorial/latched/registered inputs or outputs ?individual i/o tri-state control with polarity control ? dedicated clock/clock enable input pins (two) or programmable clocks/clock enables from i/o pins (20) ?single level 4:1 dynamic path selection (tpd = 3.0ns) ?programmable wide-mux cascade feature supports up to 16:1 mux ?programmable pull-ups, bus hold latch and open drain on i/o pins ?outputs tri-state during power-up (?ive insertion friendly) lead-free package options global routing pool (grp) i/o cells i/o pins b boundary scan control i/o cells isp control i/o pins a i/o pins c i/o pins d description the ispgdxva architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface require- ments including: multi-port multiprocessor interfaces ? ide data and address bus multiplexing (e.g. 16:1 high-speed bus mux) programmable control signal routing (e.g. interrupts, dmareqs, etc.) board-level pcb signal routing for prototyping or programmable bus interfaces the devices feature fast operation, with input-to-output signal delays (tpd) of 3.0ns and clock-to-output delays of 3.0ns. the architecture of the devices consists of a series of programmable i/o cells interconnected by a global rout- ing pool (grp). all i/o pin inputs enter the grp directly or are registered or latched so they can be routed to the required i/o outputs. i/o pin inputs are defined as four sets (a,b,c,d) which have access to the four mux inputs gdx80va_05 copyright ?2004 lattice semiconductor corporation. all brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. august 2004 t el. (503) 268-8000; 1-800-lattice; fax (503) 268-8037; http://www.latticesemi.com lead- free packag e options av ailable!
2 specifications ispgdx80va description (continued) found in each i/o cell. each output has individual, pro- grammable i/o tri-state control (oe), output latch clock (clk), clock enable (clken), and two multiplexer con- trol (mux0 and mux1) inputs. polarity for these signals is programmable for each i/o cell. the mux0 and mux1 inputs control a fast 4:1 mux, allowing dynamic selection of up to four signal sources for a given output. a wider 16:1 mux can be implemented with the mux expander feature of each i/o and a propagation delay increase of 2.0ns. oe, clk, clken, and mux0 and mux1 inputs can be driven directly from selected sets of i/o pins. optional dedicated clock input pins give minimum clock- to-output delays. clk and clken share the same set of i/o pins. clken disables the register clock when clken = 0. through in-system programming, connections between i/o pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. in keeping with its data path application focus, the ispgdxva devices contain no programmable logic arrays. all input pins include schmitt trigger buffers for noise immunity. these connections are programmed into the device using non-volatile e 2 cmos technology. non-volatile technology means the device configuration is saved even when the power is removed from the device. in addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. that is, any i/o pin configured as an input can drive one or more i/o pins configured as outputs. the device pins also have the ability to set outputs to fixed high or low logic levels (jumper or dip switch mode). device outputs are specified for 24ma sink and 12ma source current (at jedec lvttl levels) and can be tied together in parallel for greater drive. on the ispgdxva, each i/o pin is individually programmable for 3.3v or 2.5v output levels as described later. program- mable output slew rate control can be defined independently for each i/o pin to reduce overall ground bounce and switching noise. all i/o pins are equipped with ieee1149.1-compliant boundary scan test circuitry for enhanced testability. in addition, in-system programming is supported through the test access port via a special set of private com- mands. the ispgdxva i/os are designed to withstand live insertion system environments. the i/o buffers are disabled during power-up and power-down cycles. when designing for live insertion, absolute maximum rating conditions for the vcc and i/o pins must still be met. table 1. ispgdxva family members ispgdxv/va device ispgdx160v/va i/o pins 160 i/o-oe inputs* 40 i/o-clk / clken inputs* 40 i/o-muxsel1 inputs* 40 i/o-muxsel2 inputs* 40 bscan interface 4 reset t e e e e e e te ee t
3 specifications ispgdx80va architecture the ispgdxva architecture is different from traditional pld architectures, in keeping with its unique application focus. the block diagram is shown below. the program- mable interconnect consists of a single global routing pool (grp). unlike isplsi devices, there are no pro- grammable logic arrays on the device. control signals for oes, clocks/clock enables and mux controls must come from designated sets of i/o pins. the polarity of these signals can be independently programmed in each i/o cell. each i/o cell drives a unique pin. the oe control for each i/o pin is independent and may be driven via the grp by one of the designated i/o pins (i/o-oe set). the i/o-oe set consists of 25% of the total i/o pins. boundary scan test is supported by dedicated registers at each i/o pin. in-system programming is accomplished through the standard boundary scan protocol. the various i/o pin sets are also shown in the block diagram below. the a, b, c, and d i/o pins are grouped together with one group per side. i/o architecture each i/o cell contains a 4:1 dynamic mux controlled by two select lines as well as a 4x4 crossbar switch con- trolled by software for increased routing flexiability (figure 1). the four data inputs to the mux (called m0, m1, m2, and m3) come from i/o signals in the grp and/or adjacent i/o cells. each mux data input can access one quarter of the total i/os. for example, in an 80-i/o ispgdxva, each data input can connect to one of 20 i/o pins. mux0 and mux1 can be driven by designated i/o pins called muxsel1 and muxsel2. each muxsel input covers 25% of the total i/o pins (e.g. 20 out of 80). mux0 and mux1 can be driven from either muxsel1 or muxsel2. figure 1. ispgdxva i/o cell and grp detail (80 i/o device) i/ocell 0 i/o cell 1 i/o cell 38 i/o cell 39 40 i/o cells boundary scan cell bypass option i/o cell n register or latch i/o pin prog. pull-up (vccio) prog. slew rate d a b clk reset q 4-to-1 mux 80 input grp inputs vertical outputs horizontal i/o cell 79 i/o cell 78 i/o cell 41 m0 i/o group a i/o group b i/o group c i/o group d m1 4x4 crossbar switch m2 m3 mux1 mux0 global reset i/o cell 40 40 i/o cells ispgdxva architecture enhancements over ispgdx (5v) e 2 cmos programmable interconnect logic 0 logic 1 80 i/o inputs c r y0-y3 global clocks / clock_enables prog. bus hold latch clk_en from mux outputs of 2 adjacent i/o cells from mux outputs of 2 adjacent i/o cells to 2 adjacent i/o cells above to 2 adjacent i/o cells below prog. open drain 2.5v/3.3v output n+1 n+2 n-1 n-2
4 specifications ispgdx80va flexible mapping of muxsel x to mux x allows the user to change the mux select assignment after the ispgdxva device has been soldered to the board. figure 1 shows that the i/o cell can accept (by programming the appro- priate fuses) inputs from the mux outputs of four adjacent i/o cells, two above and two below. this enables cascad- ing of the muxes to enable wider (up to 16:1) mux implementations. the i/o cell also includes a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. as shown in figure 1, when the input control mux of the register/ latch selects the a path, the register/latch gets its inputs from the 4:1 mux and drives the i/o output. when selecting the b path, the register/latch is directly driven by the i/o input while its output feeds the grp. the programmable polarity clock to the latch or register can be connected to any i/o in the i/o-clk/clken set (one- quarter of total i/os) or to one of the dedicated clock input pins (y x ). the programmable polarity clock enable input to the register can be programmed to connect to any of the i/o-clk/clken input pin set or to the global clock enable inputs (clken x ). use of the dedicated clock inputs gives minimum clock-to-output delays and mini- mizes delay variation with fanout. combinatorial output mode may be implemented by a dedicated architecture bit and bypass mux. i/o cell output polarity can be programmed as active high or active low. mux expander using adjacent i/o cells the ispgdxva allows adjacent i/o cell muxes to be cascaded to form wider input muxes (up to 16 x 1) without incurring an additional full tpd penalty. however, there are certain dependencies on the locality of the adjacent muxes when used along with direct mux inputs. adjacent i/o cells expansion inputs muxout[n-2], muxout[n-1], muxout[n+1], and muxout[n+2] are fuse-selectable for each i/o cell mux. these expansion inputs share the same path as the standard a, b, c and d mux inputs, and allow adjacent i/o cell outputs to be directly connected without passing through the global routing pool. the relationship between the [n+i] adjacent cells and a, b, c and d inputs will vary depending on where the i/o cell is located on the physical die. the i/o cells can be grouped into normal and reflected i/o cells or i/o hemi- spheres. these are defined as: i/o mux operation mux1 mux0 data input selected 00 m0 01 m1 11 m2 10 m3 device normal i/o cells reflected i/o cells b9-b0, a19-a0, d19-d10 b10-b19, c0-c19, d0-d9 b19-b0, a39-a0, d39-d20 b20-b39, c0-c39, d0-d19 ispgdx80va ispgdx160va ispgdx240va b29-b0, a59-a0, d59-d30 b30-b59, c0-c59, d0-d29 table 2 shows the relationship between adjacent i/o cells as well as their relationship to direct mux inputs. note that the mux expansion is circular and that i/o cell b10, for example, draws on i/os b9 and b8, as well as b11 and b12, even though they are in different hemi- spheres of the physical die. table 2 shows some typical cases and all boundary cases. all other cells can be extrapolated from the pattern shown in the table. d10 d9 b9 b10 a0 a19 c19 c0 d19 b0 d0 b19 i/o cell 0 i/o cell 79 i/o cell 39 i/o cell 40 i/o cell index increases in this direction i/o cell index increases in this direction figure 2. i/o hemisphere configuration of ispgdx80va direct and expander input routing table 2 also illustrates the routing of mux direct inputs that are accessible when using adjacent i/o cells as inputs. take i/o cell d13 as an example, which is also shown in figure 3.
5 specifications ispgdx80va b10 b11 b12 b13 d6 d7 d8 d9 d10 d11 d12 d13 b6 b7 b8 b9 b12 b13 b14 b15 d8 d9 d10 d11 d8 d9 d10 d11 b4 b5 b6 b7 b11 b12 b13 b14 d7 d8 d9 d10 d9 d10 d11 d12 b5 b6 b7 b8 b9 b10 b11 b12 d5 d6 d7 d8 d11 d12 d13 d14 b7 b8 b9 b10 b8 b9 b10 b11 d4 d5 d6 d7 d12 d13 d14 d15 b8 b9 b10 b11 data d/ muxout data c/ muxout data b/ muxout data a/ muxout reflected i/o cells normal i/o cells table 2. adjacent i/o cells (mapping of ispgdx80va) it can be seen from figure 3 that if the d11 adjacent i/o cell is used, the i/o group a input is no longer available as a direct mux input. the ispgdxva can implement muxes up to 16 bits wide in a single level of logic, but care must be taken when combining adjacent i/o cell outputs with direct mux inputs. any particular combination of adjacent i/o cells as mux inputs will dictate what i/o groups (a, b, c or d) can be routed to the remaining inputs. by properly choosing the adjacent i/o cells, all of the mux inputs can be utilized. s0 s1 4 x 4 crossbar switch .m0 .m1 .m2 .m3 d13 i/o group a d11 mux out i/o group b d12 mux out i/o group c d14 mux out i/o group d d15 mux out ispgdx80va i/o cell figure 3. adjacent i/o cells vs. direct input path for ispgdx80va, i/o d13 special features slew rate control all output buffers contain a programmable slew rate control that provides software-selectable slew rate op- tions. open drain control all output buffers provide a programmable open-drain option which allows the user to drive system level reset, interrupt and enable/disable lines directly without the need for an off-chip open-drain or open-collector buffer. wire-or logic functions can be performed at the printed circuit board level. pull-up resistor all pins have a programmable active pull-up. a typical resistor value for the pull-up ranges from 50k ? ?
6 specifications ispgdx80va the ispgdxva family architecture has been developed to deliver an in-system programmable signal routing solution with high speed and high flexibility. the devices are targeted for three similar but distinct classes of end- system applications: programmable, random signal interconnect (prsi) this class includes pcb-level programmable signal rout- ing and may be used to provide arbitrary signal swapping between chips. it opens up the possibilities of program- mable system hardware. it is characterized by the need to provide a large number of 1:1 pin connections which are statically configured, i.e., the pin-to-pin paths do not need to change dynamically in response to control in- puts. programmable data path (pdp) this application area includes system data path trans- ceiver, mux and latch functions. with today?s 32- and 64-bit microprocessor buses, but standard data path glue components still relegated primarily to eight bits, pcbs are frequently crammed with a dozen or more data path glue chips that use valuable real estate. many of these applications consist of on-board bus and memory inter- faces that do not require the very high drive of standard glue functions but can benefit from higher integration. therefore, there is a need for a flexible means to inte- grate these on-board data path functions in an analogous way to programmable logic?s solution to control logic integration. lattice?s cplds make an ideal control logic complement to the ispgdxva in-system programmable data path devices as shown below. data path bus #1 control inputs (from p) address inputs (from p) control outputs system clock(s) data path bus #2 configuration (switch) outputs isp/jtag interface isplsi/ ispmach device ispgdxva device buffers / registers decoders buffers / registers state machines figure 4. ispgdxva complements lattice cplds applications programmable switch replacement (psr) includes solid-state replacement and integration of me- chanical dip switch and jumper functions. through in-system programming, pins of the ispgdxva devices can be driven to high or low logic levels to emulate the traditional device outputs. psr functions do not require any input pin connections. these applications actually require somewhat different silicon features. prsi functions require that the device support arbitrary signal routing on-chip between any two pins with no routing restrictions. the routing connections are static (determined at programming time) and each input-to-output path operates independently. as a result, there is little need for dynamic signal controls (oe, clocks, etc.). because the ispgdxva device will inter- face with control logic outputs from other components (such as isplsi or ispmacha) on the board (which frequently change late in the design process as control logic is finalized), there must be no restrictions on pin-to- pin signal routing for this type of application. pdp functions, on the other hand, require the ability to dynamically switch signal routing (muxing) as well as latch and tri-state output signals. as a result, the pro- grammable interconnect is used to define possible signal routes that are then selected dynamically by control signals from an external mpu or control logic. these functions are usually formulated early in the conceptual design of a product. the data path requirements are driven by the microprocessor, bus and memory architec- ture defined for the system. this part of the design is the earliest portion of the system design frozen, and will not usually change late in the design because the result would be total system and pcb redesign. as a result, the ability to accommodate arbitrary any pin-to-any pin re- routing is not a strong requirement as long as the designer has the ability to define his functions with a reasonable degree of freedom initially. as a result, the ispgdxva architecture has been defined to support psr and prsi applications (including bidirec- tional paths) with no restrictions, while pdp applications (using dynamic muxing) are supported with a minimal number of restrictions as described below. in this way, speed and cost can be optimized and the devices can still support the system designer?s needs. the following diagrams illustrate several ispgdxva ap- plications.
7 specifications ispgdx80va figure 6. data bus byte swapper figure 7. four-port memory interface control bus data bus a data bus b oea oeb i/oa d0-7 d8-15 d8-15 d0-7 i/ob xcvr oea oeb i/oa i/ob xcvr oea oeb i/oa i/ob xcvr oea oeb i/oa i/ob xcvr bus 4 bus 3 bus 2 bus 1 port #1 oe1 memory port oem sel0 sel1 to memory port #2 oe2 port #3 oe3 note: all oe and sel lines driven by external arbiter logic (not shown). port #4 oe4 4-to-1 16-bit mux bidirectional figure 5. address demultiplex/data buffering control bus muxed address data bus dq clk oea oeb i/oa i/ob address buffered data to memory / peripherals xcvr address latch applications (continued) designing with the ispgdxva as mentioned earlier, this architecture satisfies the prsi class of applications without restrictions: any i/o pin as a single input or bidirectional can drive any other i/o pin as output. for the case of pdp applications, the designer does have to take into consideration the limitations on pins that can be used as control (mux0, mux1, oe, clk) or data (muxa-d) inputs. the restrictions on control inputs are not likely to cause any major design issues because the input possibilities span 25% of the total pins. the muxa-d input partitioning requires that designers consciously assign pinouts so that mux inputs are in the appropriate, disjoint groups. for example, since the muxa group includes i/o a0-a19 (80 i/o device), it is not possible to use i/o a0 and i/o a9 in the same mux function. as previously discussed, data path functions will be assigned early in the design process and these restrictions are reasonable in order to optimize speed and cost. user electronic signature the ispgdxva family includes dedicated user elec- tronic signature (ues) e 2 cmos storage to allow users to code design-specific information into the devices to identify particular manufacturing dates, code revisions, or the like. the ues information is accessible through the boundary scan programming port via a specific com- mand. this information can be read even when the security cell is programmed. security the ispgdxva family includes a security feature that prevents reading the device program once set. even when set, it does not inhibit reading the ues or device id code. it can be erased only via a device bulk erase.
8 specifications ispgdx80va absolute maximum ratings 1,2 supply voltage v cc ................................. -0.5 to +5.4v input voltage applied ............................... -0.5 to +5.6v off-state output voltage applied ............ -0.5 to +5.6v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). 2. compliance with the thermal management section of the lattice semiconductor data book or cd-rom is a requirement. dc recommended operating conditions c symbol table 2-0006/gdxva c parameter package type dedicated clock capacitance 8 units typical test conditions 1 2 7 tqfp tqfp i/o capacitance pf pf v = 3.3v, v = 2.0v v = 3.3v, v = 2.0v cc cc y i/o capacitance (t a =25 o c, f=1.0 mhz) parameter minimum maximum units erase/reprogram cycles 10,000 ? cycles erase/reprogram specifications symbol table 2-0005/gdxva v cc v ccio parameter supply voltage i/o reference voltage commercial t a = 0 c to +70 c min. max. units 3.00 2.3 3.60 3.60 v industrial t a = -40 c to +85 c 3.00 3.60 v v
9 specifications ispgdx80va switching test conditions input pulse levels input rise and fall time input timing reference levels output timing reference levels output load gnd to v ccio(min) < 1.5ns 10% to 90% v ccio(min) /2 v ccio(min) /2 see figure 8 3-state levels are measured 0.5v from steady-state active level. output load conditions (see figure 8) test condition r1 3.3v 2.5v r2 cl a 35pf d 35pf b 35pf 35pf active high slow slew active low c 5pf 5pf 156 ? ? ? ? ? ? ? ? ? ? ? ? c. table 2-0007/gdxva v oh v ih v il parameter output low voltage output high voltage input high voltage input low voltage v cc = v cc (min) i ol = +100 a i ol = +24ma i oh = -100 a i oh = -12ma v cc = v cc (min) v oh
10 specifications ispgdx80va dc electrical characteristics for 2.5v range over recommended operating conditions v ih symbol 2.5v/gdxva v oh parameter input high voltage output high voltage v oh(min) = 0.5v was selected to avoid test problems by tester ground degradation. characterized, but not 100% tested. 2. typical values are at v cc = 3.3v and t a = 25 c. 3. i cc / mhz = (0.002 x i/o cell fanout) + 0.022. e.g. an input driving four i/o cells at 40mhz results in a dynamic i cc of approximately ((0.002 x 4) + 0.022) x 40 = 1.20ma. 4. for a typical application with 50% of i/o pins used as inputs, 50% used as outputs or bi-directionals. 5. this parameter limits the total current sinking of i/o pins surrounding the nearest gnd pin. dc char_gdx80va i pu i bhls parameter i/o active pullup current bus hold low sustaining current i ih i il input or i/o high leakage current input or i/o low leakage current 0v a i bht bus hold trip points v il ev ih v a a a 40 e e a (v ccio -0.2) = 3.3v, v out = 0.5v, t a = 25 c i ccq 4 quiescent power supply current e 12 e ma v il = 0.5v, v ih = v cc v in = v il (max) i bhhs bus hold high sustaining current -40 e e a v in = v ih (min) i bhlo bus hold low overdrive current e e 550 a 0v a 0v
11 specifications ispgdx80va 5.0 5.0 e e e e e e e e e e e e e e e e 5.0 8.5 6.0 9.5 6.0 6.0 6.0 6.0 e e 14.0 e 5.0 0.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 data prop. delay: any i/o pin to any i/o pin (4:1 mux) data prop. delay: muxsel inputs to any output (4:1 mux) clk. frequency, max. toggle clk. frequency with external feedback input latch or reg. setup time before y x input latch or reg. setup time before i/o clk. output latch or reg. setup time before y x output latch or reg. setup time before i/o clk. global clk. enable setup time before y x global clk. enable setup time before i/o clk. i/o clk. enable setup time before y x input latch or reg. hold time (y x ) input latch or reg. hold time (i/o clk.) output latch or reg. hold time (y x ) output latch or reg. hold time (i/o clk.) global clk. enable hold time (y x ) global clk. enable hold time (i/o clk.) i/o clk. enable hold time (y x ) output latch or reg. clk. (from y x ) to output delay input latch or register clk. (from y x ) to output delay output latch or reg. clk. ( from i/o pin) to output delay input latch or reg. clk. (from i/o pin) to output delay input to output enable input to output disable test oe output enable test oe output disable clock pulse duration, high clock pulse duration, low register reset delay from reset low reset pulse width output delay adder for output timings using slow slew rate output skew (tgco1 across chip) external timing parameters over recommended operating conditions ns ns mhz mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns e e 143 111 4.0 3.0 4.0 3.0 2.5 1.5 4.5 0.0 1.5 0.0 1.5 0.0 1.5 0.0 e e e e e e e e 3.5 3.5 e 10.0 e e a a e e e e e e e e e e e e e e e e a a a a b c b c e e e e d a t pd 2 t sel 2 f max (tog.) f max (ext.) t su1 t su2 t su3 t su4 t suce1 t suce2 t suce3 t h1 t h2 t h3 t h4 t hce1 t hce2 t hce3 t gco1 2 t gco2 2 t co1 2 t co2 2 t en 2 t dis 2 t toeen 2 t toedis 2 t wh t wl t rst t rw t sl t sk description parameter ( ) 1 tsu3+tgco1 units -5 min. max. 1. all timings measured with one output switching, fast output slew rate setting, except t sl . 2. the delay parameters are measured with vcc as i/o voltage reference. an additional 0.5ns delay is incurred when vccio is used as i/o voltage reference. 3. the new -3 speed grade (tpd = 3.0ns) will be effective starting with date code a113xxxx. devices with topside date codes prior to a113xxxx adhere to the shaded -3 speed grade (tpd = 3.5ns). # 3.0 3.2 e e e e e e e e e e e e e e e e 3.0 5.5 3.5 6.0 4.0 4.0 5.5 5.5 e e 7.0 e 3.0 0.5 e e 250 208.3 2.2 1.8 1.8 1.5 1.8 1.5 2.5 0.0 0.5 0.0 0.5 0.0 1.0 0.0 e e e e e e e e 2.0 2.0 e 4.5 e e -3 3 min. max. test 1 cond. 3.5 3.5 e e e e e e e e e e e e e e e e 3.5 6.0 4.0 7.0 5.0 5.0 6.0 6.0 e e 8.0 e 3.5 0.5 e e 250 166.7 3.0 2.5 2.5 2.0 2.5 1.5 3.0 0.0 0.5 0.0 1.0 0.0 1.0 0.0 e e e e e e e e 2.0 2.0 e 5.0 e e -3 min. max.
12 specifications ispgdx80va 9.0 9.0 e e e e e e e e e e e e e e e e 9.0 13.5 11.5 15.7 10.5 10.5 10.5 10.5 e e 22.0 e 9.0 1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 data prop. delay: any i/o pin to any i/o pin (4:1 mux) data prop. delay: muxsel inputs to any output (4:1 mux) clk. frequency, max. toggle clk. frequency with external feedback input latch or reg. setup time before y x input latch or reg. setup time before i/o clock output latch or reg. setup time before y x output latch or reg. setup time before i/o clk. global clk. enable setup time before y x global clk. enable setup time before i/o clk. i/o clk. enable setup time before y x input latch or reg. hold time (y x ) input latch or reg. hold time (i/o clk.) output latch or reg. hold time (y x ) output latch or reg. hold time (i/o clk.) global clk. enable hold time (y x ) global clk. enable hold time (i/o clk.) i/o clk. enable hold time (y x ) output latch or reg. clk. (from y x ) to output delay input latch or reg. clk. (from y x ) to output delay output latch or reg. clk. ( from i/o pin) to output delay input latch or reg. clock (from i/o pin) to output delay input to output enable input to output disable test oe output enable test oe output disable clk. pulse duration, high clk. pulse duration, low reg. reset delay from reset low reset pulse width output delay adder for output timings using slow slew rate output skew (tgco1 across chip) external timing parameters over recommended operating conditions ns ns mhz mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns e e 83 62.5 7.0 6.0 7.0 6.0 4.0 3.0 8.5 0.0 3.0 0.0 3.0 0.0 3.0 0.0 e e e e e e e e 6.0 6.0 e 18.0 e e a a e e e e e e e e e e e e e e e e a a a a b c b c e e e e d a t pd 2 t sel 2 f max (tog.) f max (ext.) t su1 t su2 t su3 t su4 t suce1 t suce2 t suce3 t h1 t h2 t h3 t h4 t hce1 t hce2 t hce3 t gco1 2 t gco2 2 t co1 2 t co2 2 t en 2 t dis 2 t toeen 2 t toedis 2 t wh t wl t rst t rw t sl t sk description parameter ( ) 1 tsu3+tgco1 units -9 min. max. 1. all timings measured with one output switching, fast output slew rate setting, except t sl . 2. the delay parameters are measured with vcc as i/o voltage reference. an additional 0.5ns delay is incurred when vccio is used as i/o voltage reference. # -7 min. max. test 1 cond. e e 100 80 5.5 4.5 5.5 4.5 3.5 2.5 6.5 0.0 2.5 0.0 2.5 0.0 2.5 0.0 e e e e e e e e 5.0 5.0 e 14.0 e e 7.0 7.0 e e e e e e e e e e e e e e e e 7.0 11.0 9.0 13.0 8.5 8.5 8.5 8.5 e e 18.0 e 7.0 0.5
13 specifications ispgdx80va external timing parameters (continued) 2 8 010 420304 0506 070 i/o cell fanout ? ? ?
14 specifications ispgdx80va -3 2 -3 -5 parameter # description 1 min. max. min. max. min. max. units inputs t io 32 input buffer delay ? 0.3 ? 0.4 ? 0.9 ns grp t grp 33 grp delay ? 1.1 ? 1.1 ? 1.1 ns mux t muxd 34 i/o cell mux a/b/c/d data delay ? 0.8 ? 1.0 ? 1.5 ns t muxexp 35 i/o cell mux a/b/c/d expander delay ? 1.3 ? 1.5 ? 2.0 ns t muxs 36 i/o cell data select ? 1.0 ? 1.0 ? 1.5 ns t muxsio 37 i/o cell data select (i/o clock) ? 1.5 ? 1.5 ? 3.0 ns t muxsg 38 i/o cell data select (yx clock) ? 1.5 ? 1.5 ? 2.0 ns t muxselexp 39 i/o cell mux data select expander delay ? 1.5 ? 1.5 ? 2.0 ns register t iolat 40 i/o latch delay ? 1.0 ? 1.0 ? 1.0 ns t iosu 41 i/o register setup time before clock ? 0.4 ? 0.8 ? 2.0 ns t ioh 42 i/o register hold time after clock ? 1.4 ? 1.7 ? 1.5 ns t ioco 43 i/o register clock to output delay ? 0.9 ? 1.2 ? 0.5 ns t ior 44 i/o reset to output delay ? 1.0 ? 1.0 ? 1.5 ns t cesu 45 i/o clock enable setup time before clock ? 0.6 ? 1.3 ? 2.0 ns t ceh 46 i/o clock enable hold time after clock ? 1.2 ? 1.2 ? 0.5 ns data path t fdbk 47 i/o register feedback delay ? 0.4 ? 0.4 ? 0.9 ns t iobp 48 i/o register bypass delay ? 0.0 ? 0.0 ? 0.0 ns t ioob 49 i/o register output buffer delay ? 0.0 ? 0.0 ? 0.0 ns t muxcg 50 i/o register a/b/c/d data input mux delay (yx clock) ? 1.3 ? 1.5 ? 2.0 ns t muxcio 51 i/o register a/b/c/d data input mux delay (i/o clock) ? 1.3 ? 1.5 ? 3.0 ns t iodg 52 i/o register i/o mux delay (yx clock) ? 3.1 ? 3.5 ? 4.0 ns t iodio 53 i/o register i/o mux delay (i/o clock) ? 3.1 ? 3.5 ? 5.0 ns outputs t ob 54 output buffer delay ? 0.8 ? 1.0 ? 1.5 ns t obs 55 output buffer delay (slow slew option) ? 3.8 ? 4.5 ? 6.5 ns t oeen 56 i/o cell oe to output enable ? 2.6 ? 3.5 ? 4.0 ns t oedis 57 i/o cell oe to output disable ? 2.6 ? 3.5 ? 4.0 ns t goe 58 grp output enable and disable delay ? 0.0 ? 0.0 ? 0.0 ns t toe 59 test oe enable and disable delay ? 2.5 ? 2.5 ? 2.0 ns clocks t ioclk 60 i/o clock delay ? 0.3 ? 0.3 ? 2.0 ns t gclk 61 global clock delay ? 1.3 ? 1.3 ? 2.0 ns t gclkeng 62 global clock enable (yx clock) ? 2.5 ? 2.5 ? 2.5 ns t gclkenio 63 global clock enable (i/o clock) ? 2.0 ? 2.0 ? 3.5 ns t ioclkeng 64 i/o clock enable (yx clock) ? 1.5 ? 1.5 ? 2.5 ns global reset t gr 65 global reset to i/o register latch ? 5.2 ? 6.0 ? 11.0 ns internal timing parameters over recommended operating conditions 1. internal timing parameters are not tested and are for reference only. 2. the new -3 speed grade (tpd = 3.0ns) will be effective starting with date code a113xxxx. devices with topside date codes p rior to a113xxxx adhere to the shaded -3 speed grade (tpd = 3.5ns). timing rev. 2.9
15 specifications ispgdx80va -7 -9 parameter # description 1 min. max. min. max. units inputs t io 32 input buffer delay ? 1.4 ? 1.9 ns grp t grp 33 grp delay ? 1.1 ? 1.1 ns mux t muxd 34 i/o cell mux a/b/c/d data delay ? 2.0 ? 2.5 ns t muxexp 35 i/o cell mux a/b/c/d expander delay ? 2.5 ? 3.0 ns t muxs 36 i/o cell data select ? 2.0 ? 2.5 ns t muxsio 37 i/o cell data select (i/o clock) ? 4.5 ? 6.0 ns t muxsg 38 i/o cell data select (yx clock) ? 2.5 ? 3.0 ns t muxselexp 39 i/o cell mux data select expander delay ? 2.5 ? 3.0 ns register t iolat 40 i/o latch delay ? 1.0 ? 1.0 ns t iosu 41 i/o register setup time before clock ? 3.2 ? 4.4 ns t ioh 42 i/o register hold time after clock ? 2.3 ? 2.6 ns t ioco 43 i/o register clock to output delay ? 0.5 ? 0.5 ns t ior 44 i/o reset to output delay ? 1.5 ? 1.5 ns t cesu 45 i/o clock enable setup time before clock ? 2.5 ? 2.0 ns t ceh 46 i/o clock enable hold time after clock ? 1.0 ? 2.0 ns data path t fdbk 47 i/o register feedback delay ? 1.2 ? 1.3 ns t iobp 48 i/o register bypass delay ? 0.3 ? 0.6 ns t ioob 49 i/o register output buffer delay ? 0.6 ? 0.7 ns t muxcg 50 i/o register a/b/c/d data input mux delay (yx clock) ? 2.5 ? 3.0 ns t muxcio 51 i/o register a/b/c/d data input mux delay (i/o clock) ? 4.5 ? 6.0 ns t iodg 52 i/o register i/o mux delay (yx clock) ? 5.0 ? 6.0 ns t iodio 53 i/o register i/o mux delay (i/o clock) ? 7.0 ? 9.0 ns outputs t ob 54 output buffer delay ? 2.2 ? 2.9 ns t obs 55 output buffer delay (slow slew option) ? 9.2 ? 11.9 ns t oeen 56 i/o cell oe to output enable ? 6.0 ? 7.5 ns t oedis 57 i/o cell oe to output disable ? 6.0 ? 7.5 ns t goe 58 grp output enable and disable delay ? 0.0 ? 0.0 ns t toe 59 test oe enable and disable delay ? 2.5 ? 3.0 ns clocks t ioclk 60 i/o clock delay ? 3.2 ? 4.4 ns t gclk 61 global clock delay ? 2.7 ? 3.4 ns t gclkeng 62 global clock enable (yx clock) ? 3.7 ? 5.4 ns t gclkenio 63 global clock enable (i/o clock) ? 5.7 ? 8.4 ns t ioclkeng 64 i/o clock enable (yx clock) ? 4.2 ? 6.4 ns global reset t gr 65 global reset to i/o register latch ? 13.7 ? 16.4 ns internal timing parameters 1 over recommended operating conditions 1. internal timing parameters are not tested and are for reference only. 2. refer to the timing model in this data sheet for further details. timing rev. 2.9
16 specifications ispgdx80va switching waveforms clock width clk (i/o input) t wl t wh combinatorial i/o output valid input data (i/o input) t pd t sel valid input muxsel (i/o input) combinatorial output combinatorial i/o output oe (i/o input) t en t dis i/o output enable/disable registered output reset registered i/o output t rst reset t rw i/o pin reset te e e r e e e e t t restere tt e t t
17 specifications ispgdx80va isplever development system the isplever development system supports ispgdx design using a vhdl or verilog language syntax. from creation to in-system programming, the isplever sys- tem is an easy-to-use, self-contained design tool. features vhdl and verilog synthesis support available ispgdx design compiler - design rule checker - i/o connectivity checker - automatic compiler function industry standard jedec file for programming min/max timing report interfaces to popular timing simulators user electronic signature (ues) support detailed log and report files for easy design debug on-line help w indows xp, windows 2000, windows 98 and windows nt compatible solaris and hp-ux versions available in-system programmability all necessary programming of the ispgdxva is done via four ttl level logic interface signals. these four signals are fed into the on-chip programming circuitry where a state machine controls the programming. on-chip programming can be accomplished using an ieee 1149.1 boundary scan protocol. the ieee 1149.1- compliant interface signals are test data in (tdi), test data out (tdo), test clock (tck) and test mode select (tms) control. the epen pin is also used to enable or disable the jtag port. the embedded controller port enable pin (epen) is used to enable the jtag tap controller and in that regard has similar functionality to a trst pin. when the pin is driven high, the jtag tap controller is enabled. this is also true when the pin is left unconnected, in which case the pin is pulled high by the permanent internal pullup. this allows isp programming and bscan testing to take place as specified by the instruction table. when the pin is driven low, the jtag tap controller is driven to a reset state asynchronously. it stays there while the pin is held low. after pulling the pin high the jtag controller becomes active. the intent of this fea- ture is to allow the jtag interface to be directly controlled by the data bus of an embedded controller (hence the name embedded port enable). the epen signal is used as a device select to prevent spurious programming and/or testing from occuring due to random bit patterns on the data bus. figure 9 illustrates the block diagram for the ispjtaga interface. figure 9. ispjtag device programming interface ispgdx 80va device tdo tdi tms tck epen ispjtag programming interface isplsi device ispmach device ispgdx 80va device ispgdx 80va device
18 specifications ispgdx80va boundary scan the ispgdxva devices provide ieee1149.1a test capa- bility and isp programming through a standard boundary scan test access port (tap) interface. the boundary scan circuitry on the ispgdxva family operates independently of the programmed pattern. this allows customers using boundary scan test to have full test capability with only a single bsdl file. the ispgdxva devices are identified by the 32-bit jtag idcode register. the device id assignments are listed in table 4. table 3. i/o shift register order figure 10. boundary scan register circuit for i/o pins normal function oe extest u p date dr scanout (to next cell) clock dr scanin (from previous cell shift dr normal function toe dq dq dq dq dq i/o pin reset bscan registers bscan latches highz 0 1 0 1 prog_mode extest i/o shift reg order/ispgdxva ispgdx80va tdi, toe, reset t st rester rer ee t t r s e ee
19 specifications ispgdx80va the ispjtag programming is accomplished by execut- ing lattice private instructions under the boundary scan state machine. details of the programming sequence are transparent to the user and are handled by lattice isp daisy chain 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 0 1 update-ir exit2-ir p ause-ir exit1-ir shift-ir capture-ir select-ir-scan update-dr exit2-dr p ause-dr exit1-dr shift-dr capture-dr select-dr-scan run-test/idle t est-logic-reset figure 12. boundary scan state machine figure 11. boundary scan register circuit for input-only pins downlowad software, ispcode ?c? routines or any third- party programmers. contact lattice technical support to obtain more detailed programming information. scanout (to next cell) clock dr scanin (from previous cell shift dr dq input pin boundary scan (continued)
20 specifications ispgdx80va symbol parameter min max units t btcp tck [bscan test] clock pulse width 100 e ns t btch tck [bscan test] pulse width high 50 e ns t btcl tck [bscan test] pulse width low 50 e ns t btsu tck [bscan test] setup time 20 e ns t bth tck [bscan test] hold time 25 e ns t rf tck [bscan test] rise and fall time 50 e mv/ns t btco ta p controller falling edge of clock to valid output e 25 ns t btoz ta p controller falling edge of clock to data output disable e 25 ns t btvo ta p controller falling edge of clock to data output enable e 25 ns t btcpsu bscan test capture register setup time 20 e ns t btcph bscan test capture register hold time 25 e ns t btuco bscan test update reg, falling edge of clock to valid output e 50 ns t btuoz bscan test update reg, falling edge of clock to output disable e 50 ns t btuov bscan test update reg, falling edge of clock to output enable e 50 ns figure 13. boundary scan waveforms and timing specifications tms tdi tck tdo data to be captured data to be driven out valid data valid data valid data valid data data captured btsu t bth t btcl t btch t btcp t btvo t btco t btoz t btcsu t btch t btuov t btuco t btuoz t boundary scan (continued)
21 specifications ispgdx80va i/o input/output pins e these are the general purpose bidirectional data pins. when used as outputs, each may be independently latched, registered or tristated. they can also each assume one other control function (oe, clk/clken, and muxsel as described in the text). reset t reset t reset reset r ete t e e te e t t e te ee t t e t t t t s s s t s s s ts s s t s s s s t e s s
22 specifications ispgdx80va i/o control 100 signal signal tqfp signal locations: ispgdx80va signal 100-pin tqfp reset e ete ee t t ts t e e e e e e e e e e e s s t s s t s s t reset t s r e e e e e e e e e
23 specifications ispgdx80va pin configuration: ispgdx80va ispgdx80va 100-pin tqfp pinout diagram i/o a0 i/o a1 i/o a2 i/o a3 i/o a4 gnd i/o a5 i/o a6 i/o a7 i/o a8 i/o a9 vcc i/o a10 i/o a11 i/o a12 i/o a13 i/o a14 gnd i/o a15 i/o a16 i/o a17 i/o a18 i/o a19 i/o b0 i/o b1 i/o c19 i/o c18 i/o c17 i/o c16 i/o c15 gnd i/o c14 i/o c13 i/o c12 i/o c11 i/o c10 vcc i/o c9 i/o c8 i/o c7 i/o c6 i/o c5 gnd i/o c4 i/o c3 i/o c2 i/o c1 i/o c0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 58 ispgdx80va top view data control clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel2 muxsel1 i/o d1 i/o d0 oe clk oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk data control muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 data control i/o d19 i/o d18 i/o d17 i/o d16 i/o d15 gnd i/o d14 i/o d13 i/o d12 i/o d11 reset ts ete t ee t e e e e e t
24 specifications ispgdx80va part number description ordering information 100-pin tqfp 5.0 ispgdx80va-5t100 ispgdxva 100-pin tqfp 3.0* ispgdx80va-3t100 100-pin tqfp 7.0 ispgdx80va-7t100 family ordering number package t pd (ns) commercial 100-pin tqfp 9.0 ispgdx80va-9t100i 100-pin tqfp 7.0 ispgdx80va-7t100i 100-pin tqfp 5.0 ispgdx80va-5t100i ispgdxva family ordering number package t pd (ns) industrial note: the ispgdx80va devices are dual-marked with both commercial and industrial grades. the commercial speed grade is faster, e.g. ispgdx80va-3t100-5i. *the new -3 speed grade (tpd = 3.0ns) will be effective starting with date code a113xxxx. device number grade blank = commercial i = industrial ispgdx 80va x xxxxx x speed 3 = 3.0ns tpd* 5 = 5.0ns tpd 7 = 7.0ns tpd 9 = 9.0ns tpd package t100 = 100-pin tqfp tn100 = lead-free 100-pin tqfp device family 0212/gdx80va conventional packaging lead-free packaging lead-free 100-pin tqfp 5.0 ispgdx80va-5tn100 ispgdxva lead-free 100-pin tqfp 3.0* ispgdx80va-3tn100 lead-free 100-pin tqfp 7.0 ispgdx80va-7tn100 family ordering number package t pd (ns) commercial lead- free 100-pin tqfp 9.0 ispgdx80va-9tn100i lead- free 100-pin tqfp 7.0 ispgdx80va-7tn100i lead- free 100-pin tqfp 5.0 ISPGDX80VA-5TN100I ispgdxva family ordering number package t pd (ns) industrial note: the ispgdx80va devices are dual-marked with both commercial and industrial grades. the commercial speed grade is faster, e.g. ispgdx80va-3t100-5i. *the new -3 speed grade (t pd = 3.0ns) will be effective starting with date code a113xxxx.

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